Mixed Signal Design Verification Engineer

Job Description

**Titles**

– Mixed-Signal Verification Engineer – DSP (Austin)
– Senior Mixed-Signal Engineer – Verification (Austin)
– Analog/Mixed-Signal Verification Engineer (Austin, TX)
– DSP Verification Engineer – Mixed-Signal (Austin)
– Mixed-Signal Behavioral Modeling Engineer (Austin)
– Senior AMS Verification Engineer – DSP (Austin)
– Mixed-Signal Design & Verification Specialist – UVM (Austin)
– Semiconductor Verification Engineer – Mixed-Signal/DSP (Austin)
– Mixed-Signal Functional Verification Engineer (Austin)
– IC Verification Engineer – Mixed-Signal DSP (Austin)
– Staff Engineer – Mixed-Signal Verification (Austin)

**Work Type: Full-Time | Onsite (Austin, Texas)**
**Experience Required: 5+ Years**
**Employment Type: Direct Hire (Core Team, Well-Funded Startup)**
**Sponsorship: Likely H1B/EAD eligible**
**About The Client**
**Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP solutions powering cloud and AI infrastructure. Their breakthrough DSP technology is foundational to high-speed data center interconnects — enabling faster, more efficient cloud and AI communications. Backed by $180MM investment from Kleiner Perkins, Spark Capital, Mayfield, and Fidelity, this firm is out of stealth and scaling rapidly to support the future of AI-driven connectivity.**
**Job Overview**
**The role focuses on mixed-signal verification for advanced DSP-based communication and AI interconnect chips. You’ll develop behavioral models for analog blocks, run mixed-signal dynamic verification, and collaborate with world-class analog and digital design teams to validate next-gen coherent DSP solutions.**
**Key Responsibilities**

– Perform behavioral modeling (BM) of analog designs to enable digital verification.
– Conduct mixed-signal dynamic verification (without AMS) using chip-level digital design tools.
– Write, simulate, and debug Verilog/SystemVerilog code for verification.
– Use Cadence Virtuoso Schematics to interface with analog designs.
– Develop test plans, verification strategies, and scalable testbench automation.
– Collaborate with DSP, analog, and digital engineering teams to validate high-speed designs.
– Present verification results, maintain coverage metrics, and ensure first-pass success in silicon.

**Minimum Qualifications**

– 5+ years of mixed-signal verification experience.
– Strong background in Behavioral Modelling (BM) for analog-to-digital verification.
– Hands-on Verilog/SystemVerilog verification coding.
– Familiarity with Virtuoso Schematics. Basic understanding of analog design fundamentals.

**Preferred Qualifications**

– Experience with UVM (Universal Verification Methodology).
– Background working with both Synopsys and Cadence verification tools.
– Understanding of advanced verification infrastructure – simulators, waveform viewers, coverage, execution automation.
– Proven track record of building portable/scalable test environments.
– Strong communication skills; ability to write test plans, document results, present to multi-functional teams.